interface sm4_io(input bit clock);
    logic reset_n ;
    logic key_valid;
    logic data_valid;
    logic [127:0] MK;
    logic [127:0] din;
    logic [1:0]mode_in;
    logic key_ex_finished;
    logic data_ready;
    logic [127:0] dout;

    clocking cb @(posedge clock);
        default input #1ns output #1ns;
        output reset_n;
        output key_valid;
        output data_valid;
        output MK;
        output din;
        output mode_in;
        input key_ex_finished;
        input data_ready;
        input dout;
    endclocking

    modport TB (
    clocking cb,
    output reset_n,
    output mode_in
    );






endinterface //sm4_io
